This research supports work I am doing with theoretical limitations of parallel processing, developing a unified analytical model that covers all known (non-quantum) methods for achieving parallel speedup. One result of this work is the ability to explore the state-space defined by the model in terms of maximizing performance with system/hardware support. The student contribution will be in the form of simulation that allows exploration of the state-space defined by the unified equation. The student work will be presented at a conference.

The student will develop a simulation of multiple levels of parallel processing that can be used with different parameters to mine conclusions from the analytical model. This model will NOT be a detailed hardware model with bus lines and interrupts, but a simulation of the theoretical unified parallel speedup model. Real-world instantiations of theoretical possibilities necessitate compromises and deal with physical and engineering constraints. The actual speedup values generated by the simulation will represent theoretical maximums, and are not that interesting themselves, but comparing the effect of varying parameters will be of significant interest to theoreticians and computer engineers.

One expected result is due to the diminishing returns of parallel speedup for each increment of additional hardware (and $) at each level of parallelism, understood since Amdahl's Law. Each level of parallelism represents an opportunity to start again at the efficient end of the diminishing returns curve. The maximum overall speedup should be returned with a balanced allocation of hardware ($) at each level of parallelism.

Simulation implementation language: probably JAVA

Would be nice to have a GUI front-end and be accessible over the web so others can verify my results and perform their own experiments, so perhaps JAVA would be the best language. Adding a GUI could perhaps be a second phase of the project.

The undergraduate researcher will submit this work as a poster to a conference Parallel and Distributed Techniques and Applications. The next conference is in the Spring, so the project can go this summer or fall. The simulation results will also be incorporated in journal paper proposing the unified analytical model and exploring insights derived from the model.

The student will develop a simulation of multiple levels of parallel processing that can be used with different parameters to mine conclusions from the analytical model. This model will NOT be a detailed hardware model with bus lines and interrupts, but a simulation of the theoretical unified parallel speedup model. Real-world instantiations of theoretical possibilities necessitate compromises and deal with physical and engineering constraints.

Project progress meetings will be occur throughout the semester at the discretion every two weeks or more often.

It is expected that the student will

Grading: Completion of the above tasks to the satisfaction of the instructor will determine the student grade for the course.